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In this paper, we proposed a novel light-driven polymer actuator that could produce remotely controllable tensile stroke in response to near infrared (NIR) light. The light-driven polymer actuator was composed of a twisted and coiled nylon-6 fiber (TCN) and a thin poly(3,4-ethylenedioxythiophene) doped with p-toluenesulfonate (PEDOT-Tos) layer. By adopting dip-coating methodology with thermal polymerization process, we constructed a thin and uniform PEDOT-Tos layer on the surface of the three-dimensional TCN structure. Thanks to the PEDOT-Tos layer with excellent NIR light absorption characteristic, the NIR light illumination via a small LEDs array allowed the multiple PEDOT-Tos coated TCN actuators to be photo-thermally heated to a fairly consistent temperature and to simultaneously produce a contractile strain that could be modulated as high as 8.7% with light power. The actuation performance was reversible without any significant hysteresis and highly durable during 3000 cyclic operations via repetitive control of the LEDs. Together with its simple structure and facile fabrication, the light-driven actuator can lead to technical advances in artificial muscles due to its attractive benefits from remote controllability without complex coupled instruments and electromagnetic interference.
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We investigate the interrelation between some variations and the stability of Negative Capacitance Field-Effect Transistors (NC FETs). When a variation effect is considered, stability issues which are making hysteretic operation should be considered for NC FETs as well. In this paper, to make sure of stability and hysteresis-free operation, a thickness margin of ferroelectric layer is suggested. It is the easiest solution for designing and surest method of vouching for hysteresis-free operation. Although some disadvantages which make subthreshold swing (SS) a bit higher than without a margin on thickness of ferroelectric layer (TFE) can be caused, both still high performance and stable operation can be achieved.
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In this work, the work function variation (WFV) and global variability (GV) sources on 5 nm node gate-all-around (GAA) silicon vertical field-effect transistor (VFET) devices are studied through technology computer-aided design (TCAD) simulations and spice simulation based on BSIM-CMG model. Compared to conventional lateral FET devices, VFETs can increase the gate area effectively while minimizing the loss of layout area due to their structural characteristics. Considering VFET devices below 5 nm node, an expansion of the gate area of the device reduces the influence of WFV. However, the effect of GV is exacerbated by weakening gate controllability. In order to analyze the exact variability issues, it is necessary to consider not only the influence by the WFV but also the influence by the GV. Therefore, we propose accurate guideline by analyzing the integrated variability issues in a various VFET device structures in a single device and a 6-T SRAM bit cells.
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In this paper, we investigate the impact of geometry parameters such as ferroelectric layer thickness (TFE), extension length (LExt), overlap length (Lov) on negative capacitance FET (NCFET). The NCFET is designed using HfZrO2 (HZO) ferroelectric materials and the Nanoplate FET (NPFET) presented as a next generation device. We use the 3-D TCAD Sentaurus simulator to analyze characteristics of the NCFET. The NCFET designed considering the stable condition overcomes the Boltzmann limit (i.e., the physical limit in the S.S., which is 60 mV/decade at 300 K) through the steep subthreshold swing (S.S.) and exhibits negative Drain-induced barrier lowering (DIBL) phenomenon. When examining the characteristics of NPFET and NCFET according to LExt and Lov, the NCFET exhibits gate capacitance (Cgg) tendency opposite to that of the NPFET. The NCFET with the scaled VDD has a significant advantage over the gate delay (τd). The NCFET has better performance in environments where conventional device is more vulnerable to short channel effects (SCEs).
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In this paper, lateral gate-all-around nano-plate transistors (NP-FETs) for 3.5 nm technology node were optimized and compared with other nodes such as 7 nm and 5 nm node devices. The transistors' electrostatic was analyzed using a 3D TCAD simulation. We firstly optimized physical parameters such as channel radius and thickness. The NP-FETs for 3.5 nm node had better gate controllability due to smaller channel thickness and therefore showed an advantage in subthreshold swing (S.S.). However, parasitic resistance and capacitance, and low bias condition of scaled device lowered on-current level. These problems of smaller device were also related to limitation of RC-delay performance. Accordingly, the scaled device with optimized physical parameters showed ~1% decrease in delay performance compared to 5 nm node device. In order to improve RC-delay performance, trenched contact method and channel strain engineering method were separately applied for the same device. For each engineering technique, the on-current boosting was successful, showing ~14% faster RC-delay performance with strain engineering and ~18% faster RC-delay with trenched contact method.
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Accurate evaluations of self-heating effects (SHEs) in highly down-scaled devices have become essential for improved performance and reliability of such devices. In this paper, SHEs in a triplestacked nanowire FETs (NWFETs) with trenched source drain structures, a structure which may be capable of obtaining a high on-current (Ion) in the 5 nm node, were analyzed through TCAD simulations. It was confirmed that trench methods for triple-stacked devices can effectively boost Ion if disregarding SHEs. However, because SHEs generated under high Ion prevent any increase of Ion, the trench steps should be adjusted appropriately considering the balance between the contact resistance and the SHEs. In order to obtain a proper trench depth, several steps were compared through a simulation. To support the results, the thermal resistance (Rth) was used in the comparison.
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The temperature dependency of influence of variability sources on SRAM stability were simulated and analyzed in 90 Å non-rectangular Bulk FinFET SRAM cell. RDF is the most dominant variability source. In addition, it is also shown that standard deviation of read static noise margin (σ(RSNM)) by WFV and RDF decreases with increasing temperature, whereas σ-(RSNM) by LER increases with increasing temperature. Finally, the analyses on the simulation results mentioned above were performed.
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This paper presents an analysis of the Random Telegraph Noise (RTN) of the Gate-Induced Drain Leakage (GIDL) of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The RTN data that was measured and analytical equations are used to extract the values of the parameters for the vertical distance of the oxide trap from the interface and of the energy level of the interface trap. These values and equations allow for the distance r between the interface trap and the oxide trap to be extracted. For the first time, the accurate field enhancement factor γ(F), which depends on the magnitude of the electric field at the Si/SiO2 interface, was used to calculate the current ratio before and after the electron trapping, and the value extracted for r is completely different depending on the enhancement factor that is used.
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In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.