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Molybdenum disulfide (MoS2) is a promising candidate for next-generation transistor channel materials, boasting outstanding electrical properties and ultrathin structure. Conventional ion implantation processes are unsuitable for atomically thin two-dimensional (2D) materials, necessitating nondestructive doping methods. We proposed a novel approach: tunable n-type doping through sulfur vacancies (VS) and p-type doping by nitrogen substitution in MoS2, controlled by the duration of NH3 plasma treatment. Our results reveal that NH3 plasma exposure of 20 s increases the 2D sheet carrier density (n2D) in MoS2 field-effect transistors (FETs) by +4.92 × 1011 cm-2 at a gate bias of 0 V, attributable to sulfur vacancy generation. Conversely, treatment of 40 s reduces n2D by -3.71 × 1011 cm-2 due to increased nitrogen doping. X-ray photoelectron spectroscopy, Raman spectroscopy, and photoluminescence analyses corroborate these electrical characterization results, indicating successful n- and p-type doping. Temperature-dependent measurements show that the Schottky barrier height at the metal-semiconductor contact decreases by -31 meV under n-type conditions and increases by +37 meV for p-type doping. This study highlights NH3 plasma treatment as a viable doping method for 2D materials in electronic and optoelectronic device engineering.
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This paper investigates the threshold voltage shift (ΔVTH) induced by positive bias temperature instability (PBTI) in silicon carbide (SiC) power MOSFETs. By analyzing ΔVTH under various gate stress voltages (VGstress) at 150 °C, distinct mechanisms are revealed: (i) trapping in the interface and/or border pre-existing defects and (ii) the creation of oxide defects and/or trapping in spatially deeper oxide states with an activation energy of ~80 meV. Notably, the adoption of different characterization methods highlights the distinct roles of these mechanisms. Moreover, the study demonstrates consistent behavior in permanent ΔVTH degradation across VGstress levels using a power law model. Overall, these findings deepen the understanding of PBTI in SiC MOSFETs, providing insights for reliability optimization.
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Integrated electrochromic devices powered by photovoltaic cells have evoked a lot of interest due to their promising commercial prospects. However, their application has been restricted by the voltage adaption between the self-powered voltage and the color-changing threshold voltage (Vt). Herein, a strategy of bidirectional voltage regulating is proposed to develop a novel stand-alone integrated photovoltachromic device (I-PVCD), which integrates perovskite/organic tandem solar cells (P/O-TSCs) to drive color-changing process of conjugated poly(3-hexylthiophene) (P3HT) films. To lower the driving-voltage of electrochromic layer, C60 is introduced to decrease the onset oxidation potential of P3HT film, and thus leading to a reduced Vt of 0.70 V benefiting from the enhanced highest occupied molecular orbital level and decreased charge transfer resistance from 67.46 to 49.89 Ω. Simultaneously, PBDB-T is utilized as the hole transport layer in the interconnecting layer of CsPbI2Br/PTB7-Th:IEICO-4F P/O-TSC to improve its open-circuit voltage (Voc) to 1.85 V. Under their synergetic merits, a I-PVCD with a wider self-adaptive voltage range is achieved. This device can undergo fast and reversible chromic transition from beautiful magenta to transparent only under the solar radiation, and demonstrates a coloration efficiency of 351.90 cm2 C-1 and a switching time of 2 s besides its excellent operating reliability.
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Herein, a heterojunction structure integrating p-type tellurium (Te) and n-type aluminum-doped indium-zinc-tin oxide (Al:IZTO) is shown to precisely modulate the threshold voltage (VT) of the oxide thin-film transistor (TFT). The proposed architecture integrates Te as an electron-blocking layer and Al:IZTO as a charge-carrier transporting layer, thereby enabling controlled electron injection. The effects of incorporating the Te layer onto Al:IZTO are investigated, with a focus on X-ray photoelectron spectroscopy (XPS) analysis, in order to explain the behavior of oxygen vacancies and to depict the energy band structure configurations. By modulating the thickness and employing both single and double deposition methods for the heterojunction Te layer, a remarkable VT shift of up to +20 V is achieved. Furthermore, this study also shows excellent stability to a positive bias stress of +2 MV/cm for 10,000 s without additional passivation layers, demonstrating the robustness of the designed TFT. By a thorough optimization of the Al:IZTO/Te interface, the results demonstrate not only the substantial impact of the introduced heterojunction structure on VT control but also the endurance, durability, and stability of the optimized TFTs under prolonged long-term operating stress, thus offering promising prospects for tailored semiconductor device applications.
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Organic electrochemical transistors (OECTs) are of great interest in low-power bioelectronics and neuromorphic computing, as they utilize organic mixed ionic-electronic conductors (OMIECs) to transduce ionic signals into electrical signals. However, the poor environmental stability of OMIEC materials significantly restricts the practical application of OECTs. Therefore, the non-fused planar naphthalenediimide (NDI)-dialkoxybithiazole (2Tz) copolymers are fine-tuned through varying ethylene glycol (EG) side chain lengths from tri(ethylene glycol) to hexa(ethylene glycol) (namely P-XO, X = 3-6) to achieve OECTs with high-stability and low threshold voltage. As a result, the NDI-2Tz copolymers exhibit ambipolarity, rapid response (<10 ms), and ultra-high n-type stability. Notably, the P-6O copolymers display a threshold voltage as low as 0.27 V. They can operate in n-type mode in an aqueous solution for over 60 h, maintaining an on-off ratio of over 105. This work sheds light on the design of exceptional n-type/ambipolar materials for OECTs. It demonstrates the potential of incorporating these ambipolar polymers into water-operational integrated circuits for long-term biosensing systems and energy-efficient brain-inspired computing.
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This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.
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This study demonstrates a particular composited barrier structure of high-electron-mobility transistors (HEMTs) with an enhancement mode composed of p-GaN/GaN/AlN/AlGaN/GaN. The purpose of the composite barrier structure device is to increase the maximum drain current, reduce gate leakage, and achieve lower on-resistance (Ron) performance. A comparison was made between the conventional device without the composited barrier and the device with the composited barrier structure. The maximum drain current is significantly increased by 37%, and Ron is significantly reduced by 23%, highlighting the synergistic impact of the composite barrier structure on device performance improvement. This reason can be attributed to the undoped GaN (u-GaN) barrier layer beneath p-GaN, which was introduced to mitigate Mg diffusion in the capping layer, thus addressing its negative effects. Furthermore, the AlN barrier layer exhibits enhanced electrical properties, which can be attributed to the critical role of high-energy-gap properties that increase the 2DEG carrier density and block leakage pathways. These traps impact the device behavior mechanism, and the simulation for a more in-depth analysis of how the composited barrier structure brings improvement is introduced using Synopsys Sentaurus TCAD.
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The Vth stability and gate reliability of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O2 plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al2O3 with the alternating O2 plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O2 plasma treatment demonstrated remarkable advantages in higher Vth stability under high-temperature and long-term gate bias stress.
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The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications.
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Atomically thin oxide semiconductors are emerging as potential materials for their potentiality in monolithic 3D integration and sensor applications. In this study, a charge transfer method employing viologen, an organic compound with exceptional reduction potential among n-type organics, is presented to modulate the carrier concentration in atomically thin In2O3 without the need of annealing. This study highlights the critical role of channel thickness on doping efficiency, revealing that viologen charge transfer doping is increasingly pronounced in thinner channels owing to their increased surface-to-volume ratio. Upon viologen doping, an electron sheet density of 6.8 × 1012 cm-2 is achieved in 2 nm In2O3 back gate device while preserving carrier mobility. Moreover, by the modification of the functional groups, viologens can be conveniently removed with acetone and an ultrasonic cleaner, making the viologen treatment a reversible process. Based on this doping scheme, we demonstrate an n-type metal oxide semiconductor inverter with viologen-doped In2O3, exhibiting a voltage gain of 26 at VD = 5 V. This complementary pairing of viologen and In2O3 offers ease of control over the carrier concentration, making it suitable for the next-generation electronic applications.
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Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).
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The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.
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This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor-capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO's transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of -123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of -194.82 dBc/Hz.
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GaN devices are nowadays attracting global attention due to their outstanding performance in high voltage, high frequency, and anti-radiation ability. Research on total ionizing dose and annealing effects on E-mode GaN Cascode devices has been carried out. The Cascode device consists of a low-voltage MOSFET and a high-voltage depletion-mode GaN MISHEMT. Cascode devices of both conventional processed MOSFET and radiation-hardened MOSFET devices are fabricated to observe the TID effects. Experiment results indicate that, for the Cascode device with conventional processed MOSFET, the VTH shifts to negative values at 100 krad(Si). For the Cascode device with radiation-hardened MOSFET, the VTH shifts by -0.5 V at 100 krad(Si), while shifts to negative values are 500 krad(Si). The annealing process, after the TID experiment, shows that it can release trapped charges and help VTH recover. On one hand, the VTH shift and recover trends are similar to those of a single MOSFET device, suggesting that the MOSFET is the vulnerable part in the Cascode which determines the anti-TID ability of the device. On the other hand, the VTH shift amount of the Cascode device is much larger than that of a previously reported p-GaN HEMT device, indicating that GaN material shows a better anti-TID ability than Si.
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In today's digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices' critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device's electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device.
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Hydrophobic conjugated polymers have poor ionic transport property, so hydrophilic side chains are often grafted for their application as organic electrochemical transistors (OECTs). However, this modification lowers their charge transport ability. Here, an ionic gel interfacial layer is applied to improve the ionic transport while retaining the charge transport ability of the polymers. By using the ionic gels comprising gel matrix and ionic liquids as the interfacial layers, the hydrophobic polymer achieves the OECT feature with high transconductance, low threshold voltage, high current on/off ratio, short switching time, and high operational stability. The working mechanism is also revealed. Moreover, the OECT performance can be tuned by varying the types and ratios of ionic gels. With the proposed ionic gel strategy, OECTs can be effectively realized with hydrophobic conjugated polymers.
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In recent years, the active-matrix organic light-emitting diode (AMOLED) displays have been greatly required. A voltage compensation pixel circuit based on an amorphous indium gallium zinc oxide thin-film transistor is presented for AMOLED displays. The circuit is composed of five transistors-two capacitors (5T2C) in combination with an OLED. In the circuit, the threshold voltages of both the transistor and the OLED are extracted simultaneously in the threshold voltage extraction stage, and the mobility-related discharge voltage is generated in the data input stage. The circuit not only can compensate the electrical characteristics variation, i.e., the threshold voltage variation and mobility variation, but also can compensate the OLED degradation. Furthermore, the circuit can prevent the OLED flicker, and can achieve the wide data voltage range. The circuit simulation results show that the OLED current error rates (CERs) are lower than 3.89% when the transistor's threshold voltage variation is ±0.5V, lower than 3.49% when the mobility variation is ±30%.
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In this study, we present a detailed analysis of trapping characteristics at the AlxGa1-xN/GaN interface of AlxGa1-xN/GaN high-electron-mobility transistors (HEMTs) with reliability assessments, demonstrating how the composition of the Al in the AlxGa1-xN barrier impacts the performance of the device. Reliability instability assessment in two different AlxGa1-xN/GaN HEMTs [x = 0.25, 0.45] using a single-pulse ID-VD characterization technique revealed higher drain-current degradation (∆ID) with pulse time for Al0.45Ga0.55N/GaN devices which correlates to the fast-transient charge-trapping in the defect sites near the interface of AlxGa1-xN/GaN. Constant voltage stress (CVS) measurement was used to analyze the charge-trapping phenomena of the channel carriers for long-term reliability testing. Al0.45Ga0.55N/GaN devices exhibited higher-threshold voltage shifting (∆VT) caused by stress electric fields, verifying the interfacial deterioration phenomenon. Defect sites near the interface of the AlGaN barrier responded to the stress electric fields and captured channel electrons-resulting in these charging effects that could be partially reversed using recovery voltages. The quantitative extraction of volume trap density (Nt) using 1/f low-frequency noise characterizations unveiled a 40% reduced Nt for the Al0.25Ga0.75N/GaN device, further verifying the higher trapping phenomena in the Al0.45Ga0.55N barrier caused by the rougher Al0.45Ga0.55N/GaN interface.
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A novel monocrystalline AlN interfacial layer formation method is proposed to improve the device performance of the fully recessed-gate Al2O3/AlN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs), which is achieved by plasma-enhanced atomic layer deposition (PEALD) and in situ N2 plasma annealing (NPA). Compared with the traditional RTA method, the NPA process not only avoids the device damage caused by high temperatures but also obtains a high-quality AlN monocrystalline film that avoids natural oxidation by in situ growth. As a contrast with the conventional PELAD amorphous AlN, C-V results indicated a significantly lower interface density of states (Dit) in a MIS C-V characterization, which could be attributed to the polarization effect induced by the AlN crystal from the X-ray Diffraction (XRD) and Transmission Electron Microscope (TEM) characterizations. The proposed method could reduce the subthreshold swing, and the Al2O3/AlN/GaN MIS-HEMTs were significantly enhanced with ~38% lower on-resistance at Vg = 10 V. What is more, in situ NPA provides a more stable threshold voltage (Vth) after a long gate stress time, and ΔVth is inhibited by about 40 mV under Vg,stress = 10 V for 1000 s, showing great potential for improving Al2O3/AlN/GaN MIS-HEMT gate reliability.
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In this paper, we present a threshold-voltage extraction method for zinc oxide (ZnO) thin-film transistors (TFTs). Bottom-gate atomic-layer-deposited ZnO TFTs exhibit typical n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, unreliable threshold voltage. We posit that this obscure threshold voltage is attributed to the localized trap states of ZnO TFTs, of which the field-effect mobility can be expressed as a gate-bias-dependent power law. Hence, we derived the current-voltage relationship by dividing the drain current with the transconductance to rule out the gate-bias-dependent factors and successfully extract the reliable threshold voltage. Furthermore, we investigated the temperature-dependent characteristics of the ZnO TFTs to validate that the observed threshold voltage was genuine. Notably, the required activation energies from the low-temperature measurements displayed an abrupt decrease at the threshold voltage, which was attributed to the conduction route change from diffusion to drift. Thus, we conclude that the reliable threshold voltage of accumulation-mode ZnO TFTs can be determined using a gate-bias-dependent factor-removed current-voltage relationship with a low-temperature analysis.