RESUMEN
The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by the use of optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable the evaluation of the technologies in terms of manufacturability. The system combines fiber, free space, and planar integrated optical waveguide technologies to augment the electronic memory and the processor components. Modeling and simulation techniques were developed toward the analysis and design of board-integrated waveguide transmission characteristics and optical interfacing. We describe the fabrication, assembly, and simulation of the major components within the system.
RESUMEN
The high bandwidth available in optoelectronic interconnects is often suggested as making them suitable for use in high-performance computer systems. However, it will be shown that for problems where message sizes are small, the latency of an optoelectronic interprocessor interconnect will place a lower limit on the number of processors required to produce performance enhancement over a traditional electronic interconnect.
RESUMEN
An optoelectronic neural network is presented that is designed to solve the assignment problem--or any similar optimization task given minimal adjustment--in both crossbar and banyan packet switches. We examine the design decisions made at the hardware, software, and algorithmic levels and indicate the associated effect on the system as a whole. Clearly detailed experimental results show the system's robustness and performance due to the particular optoelectronic-algorithm combination used. The integration and packaging of such a system are also briefly discussed.