A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

Sheu, Ming-Hwa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S M Salahuddin; Lin, Jin-Fa

Sheu, Ming-Hwa; Tsai, Chang-Ming; Tsai, Ming-Yan; Hsia, Shih-Chang; Morsalin, S M Salahuddin; Lin, Jin-Fa.

Afiliación

Sheu MH; Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Tsai CM; Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Tsai MY; Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Hsia SC; Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Morsalin SMS; Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Lin JF; Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan.

Sensors (Basel) ; 21(19)2021 Oct 02.

Article en En | MEDLINE | ID: mdl-34640911

Palabras clave

bit-cell; half-select disturbance; low power; static random-access memory; sub-threshold voltage

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Texto completo: 1 Colección: 01-internacional Base de datos: MEDLINE Idioma: En Revista: Sensors (Basel) Año: 2021 Tipo del documento: Article País de afiliación: Taiwán Pais de publicación: Suiza

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