Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique.

Li, Bingyi; Shi, Hao; Chen, Liang; Yu, Wenyue; Yang, Chen; Xie, Yizhuang; Bian, Mingming; Zhang, Qingjun; Pang, Long

Li, Bingyi; Shi, Hao; Chen, Liang; Yu, Wenyue; Yang, Chen; Xie, Yizhuang; Bian, Mingming; Zhang, Qingjun; Pang, Long.

Afiliación

Li B; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. libingyi_bit@bit.edu.cn.
Shi H; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. shihao@tsinghua.edu.cn.
Chen L; Department of Electronic Engineering, Tsinghua University, Beijing 100084, China. shihao@tsinghua.edu.cn.
Yu W; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. chenl@bit.edu.cn.
Yang C; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. yuwenyue@racobit.com.
Xie Y; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. yangchen@bit.edu.cn.
Bian M; Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. xyz551_bit@bit.edu.cn.
Zhang Q; Beijing Institute of Spacecraft System Engineering, Beijing 100094, China. bianmingming2008@163.com.
Pang L; Beijing Institute of Spacecraft System Engineering, Beijing 100094, China. ztzhangqj@163.com.

Sensors (Basel) ; 18(3)2018 Feb 28.

Article en En | MEDLINE | ID: mdl-29495637

RESUMEN

With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal of the on-board SAR imaging system design is to achieve high real-time processing performance under severe size, weight, and power consumption constraints. This paper presents a multi-node prototype system for real-time SAR imaging processing. We decompose the commonly used chirp scaling (CS) SAR imaging algorithm into two parts according to the computing features. The linearization and logic-memory optimum allocation methods are adopted to realize the nonlinear part in a reconfigurable structure, and the two-part bandwidth balance method is used to realize the linear part. Thus, float-point SAR imaging processing can be integrated into a single Field Programmable Gate Array (FPGA) chip instead of relying on distributed technologies. A single-processing node requires 10.6 s and consumes 17 W to focus on 25-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. The design methodology of the multi-FPGA parallel accelerating system under the real-time principle is introduced. As a proof of concept, a prototype with four processing nodes and one master node is implemented using a Xilinx xc6vlx315t FPGA. The weight and volume of one single machine are 10 kg and 32 cm × 24 cm × 20 cm, respectively, and the power consumption is under 100 W. The real-time performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging.

Palabras clave

multi-nodes parallel accelerating technique; real-time processing; single FPGA node imaging processing; synthetic aperture radar (SAR)

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Texto completo: 1 Colección: 01-internacional Base de datos: MEDLINE Idioma: En Revista: Sensors (Basel) Año: 2018 Tipo del documento: Article País de afiliación: China Pais de publicación: Suiza

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