RESUMO
In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss. The SHA-256 algorithm is used to tackle these requirements. Current hardware architecture works present issues regarding real-time balance among processing, efficiency and cost, because some of them introduce significant critical paths. Besides, the SHA-256 algorithm itself considers no verification mechanisms for internal calculations and failure prevention. Hardware implementations can be affected by diverse problems, ranging from physical phenomena to interference or faults inherent to data spectra. Previous works have mainly addressed this problem through three kinds of redundancy: information, hardware, or time. To the best of our knowledge, pipelining has not been previously used to perform different hash calculations with a redundancy topic. Therefore, in this work, we present a novel hybrid architecture, implemented on a 3-stage pipeline structure, which is traditionally used to improve performance by simultaneously processing several blocks; instead, we propose using a pipeline technique for implementing hardware and time redundancies, analyzing hardware resources and performance to balance the critical path. We have improved performance at a certain clock speed, defining a data flow transformation in several sequential phases. Our architecture reported a throughput of 441.72 Mbps and 2255 LUTs, and presented an efficiency of 195.8 Kbps/LUT.
RESUMO
This paper proposes an approach to the real time simulation of photovoltaic (PV) arrays that are subjected to mismatching conditions, e.g. partial shadowing. The method, which has been named Model by Zone (MbZ), adopts the best PV model depending on the operating conditions of the cells in the module: it switches among single-diode model (SDM), linear model and constant voltage model. An optimized digital hardware architecture exploiting parallelism of operations over a FPGA system is exploited to effectively implement the proposed model. It reduces the computation time and the use of hardware resources. The good trade-off between accuracy and computation time of the proposed technique has been demonstrated in two cases of study: by evaluating the long-term PV power production of a PV field subjected to dynamic shadowing conditions and by analyzing the model performance in a maximum power point tracking (MPPT) application. In the former case, the proposed approach improves the computation time by 182.5 % with respect to methods that are available in recent literature, with a Relative Error (RE) at the Global Maximum Power Point (GMPP) lower than 0.39 % . In the MPPT application, the proposed technique allows to achieve a MAPE of 0.0319 % and 0.1892 % in the string voltage and power calculation, respectively.