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This paper presents an energy-efficient and high-accuracy sampling synchronization approach for real-time synchronous data acquisition in wireless sensor networks (saWSNs). A proprietary protocol based on time-division multiple access (TDMA) and deep energy-efficient coding in sensor firmware is proposed. A real saWSN model based on 2.4 GHz nRF52832 system-on-chip (SoC) sensors was designed and experimentally tested. The obtained results confirmed significant improvements in data synchronization accuracy (even by several times) and power consumption (even by a hundred times) compared to other recently reported studies. The results demonstrated a sampling synchronization accuracy of 0.8 µs and ultra-low power consumption of 15 µW per 1 kb/s throughput for data. The protocol was well designed, stable, and importantly, lightweight. The complexity and computational performance of the proposed scheme were small. The CPU load for the proposed solution was <2% for a sampling event handler below 200 Hz. Furthermore, the transmission reliability was high with a packet error rate (PER) not exceeding 0.18% for TXPWR ≥ -4 dBm and 0.03% for TXPWR ≥ 3 dBm. The efficiency of the proposed protocol was compared with other solutions presented in the manuscript. While the number of new proposals is large, the technical advantage of our solution is significant.

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This study introduces a lightweight storage system for wearable devices, aiming to optimize energy efficiency in long-term and continuous monitoring applications. Utilizing Direct Memory Access and the Serial Peripheral Interface protocol, the system ensures efficient data transfer, significantly reduces energy consumption, and enhances the device autonomy. Data organization into Time Block Data (TBD) units, rather than files, significantly diminishes control overhead, facilitating the streamlined management of periodic data recordings in wearable devices. A comparative analysis revealed marked improvements in energy efficiency and write speed over existing file systems, validating the proposed system as an effective solution for boosting wearable device performance in health monitoring and various long-term data acquisition scenarios.

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Compact, energy-efficient, and autonomous wireless sensor nodes offer incredible versatility for various applications across different environments. Although these devices transmit and receive real-time data, efficient energy storage (ES) is crucial for their operation, especially in remote or hard-to-reach locations. Rechargeable batteries are commonly used, although they often have limited storage capacity. To address this, ultra-low-power design techniques (ULPDT) can be implemented to reduce energy consumption and prolong battery life. The Energy Harvesting Technique (EHT) enables perpetual operation in an eco-friendly manner, but may not fully replace batteries due to its intermittent nature and limited power generation. To ensure uninterrupted power supply, devices such as ES and power management unit (PMU) are needed. This review focuses on the importance of minimizing power consumption and maximizing energy efficiency to improve the autonomy and longevity of these sensor nodes. It examines current advancements, challenges, and future direction in ULPDT, ES, PMU, wireless communication protocols, and EHT to develop and implement robust and eco-friendly technology solutions for practical and long-lasting use in real-world scenarios.

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This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

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Recently, there has been increased interest in adopting novel sensing technologies for continuously monitoring structural systems. In this respect, micro-electrical mechanical system (MEMS) sensors are widely used in several applications, including structural health monitoring (SHM), in which accelerometric samples are acquired to perform modal analysis. Thanks to their significantly lower cost, ease of installation in the structure, and lower power consumption, they enable extensive, pervasive, and battery-less monitoring systems. This paper presents an innovative high-performance device for SHM applications, based on a low-noise triaxial MEMS accelerometer, providing a guideline and insightful results about the opportunities and capabilities of these devices. Sensor nodes have been designed, developed, and calibrated to meet structural vibration monitoring and modal identification requirements. These components include a protocol for reliable command dissemination through network and data collection, and improvements to software components for data pipelining, jitter control, and high-frequency sampling. Devices were tested in the lab using shaker excitation. Results demonstrate that MEMS-based accelerometers are a feasible solution to replace expensive piezo-based accelerometers. Deploying MEMS is promising to minimize sensor node energy consumption. Time and frequency domain analyses show that MEMS can correctly detect modal frequencies, which are useful parameters for damage detection. The acquired data from the test bed were used to examine the functioning of the network, data transmission, and data quality. The proposed architecture has been successfully deployed in a real case study to monitor the structural health of the Marcus Aurelius Exedra Hall within the Capitoline Museum of Rome. The performance robustness was demonstrated, and the results showed that the wired sensor network provides dense and accurate vibration data for structural continuous monitoring.

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Micro-energy harvesting (MEH) is a technology of renewable power generation which is a key technology for hosting the future low-powered electronic devices for wireless sensor networks (WSNs) and, the Internet of Things (IoT). Recent technological advancements have given rise to several resources and technologies that are boosting particular facets of society. Many researchers are now interested in studying MEH systems for ultra-low power IoT sensors and WSNs. A comprehensive study of IoT will help to manage a single MEH as a power source for multiple WSNs. The popular database from Scopus was used in this study to perform a review analysis of the MEH system for ultra-low power IoT sensors. All relevant and important literature studies published in this field were statistically analysed using a review analysis method by VOSviewer software, and research gaps, challenges and recommendations of this field were investigated. The findings of the study indicate that there has been an increasing number of literature studies published on the subject of MEH systems for IoT platforms throughout time, particularly from 2013 to 2023. The results demonstrate that 67% of manuscripts highlight problem-solving, modelling and technical overview, simulation, experimental setup and prototype. In observation, 27% of papers are based on bibliometric analysis, systematic review, survey, review and based on case study, and 2% of conference manuscripts are based on modelling, simulation, and review analysis. The top-cited articles are published in 5 different countries and 9 publishers including IEEE 51%, Elsevier 16%, MDPI 10% and others. In addition, several MEH system-related problems and challenges are noted to identify current limitations and research gaps, including technical, modelling, economic, power quality, and environmental concerns. Also, the study offers guidelines and recommendations for the improvement of future MEH technology to increase its energy efficiency, topologies, design, operational performance, and capabilities. This study's detailed information, perceptive analysis, and critical argument are expected to improve MEH research's viable future.

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Metal oxide gas sensors usually require a few tens of milliwatts of power consumption to operate at high temperature, which limits their application in mobile and portable devices. Here, we proposed a cantilever structure to build an ultra-low power gas sensor for hydrogen sulfide gas detection. By employing a nano-film size effect to reduce the thermal conductivity of the material, and self-heated corrugation configuration, the power consumption of the gas sensor is significantly reduced. Through numerical analysis and finite element simulation, two different gas sensors were designed and the power consumption and stress distribution were analyzed and optimized. Under the operating temperature of 200 °C, only 0.27 mW power is consumed, the stress value is less than 250 MPa and the displacement is a few hundred of nanometers. The results serve as a guide and reference for ultra-low power MEMS device designs.

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The rapid growth of Artificial Intelligence and Internet of Things (AIoT) demands the development of ultra-low-power devices for future advanced technology. In this study, we introduce a capacitive piezotronic sensor specifically designed for tactile sensing, which enables an ultra-low-voltage operation at nearly 0 reading bias conditions with a consistent response within a wide voltage range. This sensor directly detects capacitance changes induced by piezocharges, reflecting perturbation of the effective depletion width, and ensures ultralow power capability by eliminating the necessity of turning on the Schottky diode for the first time. The dynamic response of the sensor demonstrates ultralow power capability and immunity to triboelectric interference, making it particularly suitable for tactile sensing applications in robotics, prosthetics, and wearables. This study provides valuable insights and design guidelines for future ultra-low-power thin-film-based capacitive piezotronic/piezophototronic devices for tactile sensing.

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Wake-up receivers are gaining importance in power-aware wireless sensor networks, as they significantly reduce power consumption during RF reception, enabling asynchronous communication with low latency. However, the performance of wake-up receivers still lags behind that of off-the-shelf RF transceivers. There is a growing demand for higher sensitivity, enhanced reliability, and lower latency while maintaining the lowest power consumption. In this article, our goal is to advance the performance of wake-up receivers based on off-the-shelf components and low-frequency pattern matchers. Through a systematic investigation, we proposed multiple improvements aimed at enhancing wake-up receiver performance and reliability. We introduced an improved passive envelope detector and realized a wake-up receiver for the 868 MHz band, which achieves a power consumption of 5.71 µW and latency of 9.02 ms. Our proposed wake-up receiver is capable of detecting signals down to an average power level of -61.6 dBm. These achievements represent significant advancements compared to the existing state of research on wake-up receivers based on low-frequency pattern matchers. Recent articles have not been able to attain such improved values in signal detection, power consumption, and latency.

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This paper presents a temperature compensated RC oscillator (TC-RCO) designed in 130 nm CMOS technology using regular VTH transistors. The TC-RCO uses constant transconductance gm biasing for first order temperature compensation. Device mismatch based offset correction and delay compensation techniques in the comparator are used to improve temperature instability by cancelling out second order effects. The oscillator achieves a minimum temperature stability down to 21 ppm/°C for a temperature range of -20 to 100 °C. In the lowest power mode, the oscillator consumes 254 nW power with a 1 V supply. The TC-RCO is operated in two modes, a low power mode that consumes an average of 254 nW and a high stability mode that consumes an average of 345 nW. A duty-cycling technique is used to correct offset after four cycles of oscillation. The oscillator exhibits long term stability of 10 ppm after 1 s integration time.

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An easy-plane FeSi3.5 composite with excellent magnetic properties and loss properties at MHz were proposed. The easy-plane FeSi3.5 composite has ultra-low loss at 10 MHz and 4 mT, about 372.88 kW/m3. In order to explore the reason that the Pcv of easy-plane FeSi3.5 composite is ultra-low, a none easy-plane FeSi3.5 composite, without easy-plane processing as a control group, measured the microstructure, and the magnetic and loss properties. We first found that the real reason why magnetic materials do not work properly at MHz due to overheat is dramatical increase of the excess loss and the easy-plane composite can greatly re-duce the excess loss by loss measurement and separation. The total loss of none easy-plane FeSi3.5 composite is much higher than that of easy-plane FeSi3.5 composite, where the excess loss is a major part in the total loss and even over 80% in the none easy-plane FeSi3.5 composite. The easy-plane FeSi3.5 composite can greatly reduce the total loss compared to the none easy-plane FeSi3.5 composite, from 2785.8 kW/m3 to 500.42 kW/m3 (3 MHz, 8 mT), with the main reduction being the excess loss, from 2435.2 kW/m3 to 204.93 kW/m3 (3 MHz, 8 mT), reduced by 91.58%. Furthermore, the easy-plane FeSi3.5 composite also has excellent magnetic properties, high permeability and ferromagnetic resonance frequencies. This makes the easy-plane FeSi3.5 composite become an excellent soft magnetic composite and it is possible for magnetic devices to operate properly at higher frequencies, especially at the MHz band and above.

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Photoactivated gas sensors that are fully integrated with micro light-emitting diodes (µLED) have shown great potential to substitute conventional micro/nano-electromechanical (M/NEMS) gas sensors owing to their low power consumption, high mechanical stability, and mass-producibility. Previous photoactivated gas sensors mostly have utilized ultra-violet (UV) light (250-400 nm) for activating high-bandgap metal oxides, although energy conversion efficiencies of gallium nitride (GaN) LEDs are maximized in the blue range (430-470 nm). This study presents a more advanced monolithic photoactivated gas sensor based on a nanowatt-level, ultra-low-power blue (λpeak  = 435 nm) µLED platform (µLP). To promote the blue light absorbance of the sensing material, plasmonic silver (Ag) nanoparticles (NPs) are uniformly coated on porous indium oxide (In2 O3 ) thin films. By the plasmonic effect, Ag NPs absorb the blue light and spontaneously transfer excited hot electrons to the surface of In2 O3 . Consequently, high external quantum efficiency (EQE, ≈17.3%) and sensor response (ΔR/R0 (%) = 1319%) to 1 ppm NO2 gas can be achieved with a small power consumption of 63 nW. Therefore, it is highly expected to realize various practical applications of mobile gas sensors such as personal environmental monitoring devices, smart factories, farms, and home appliances.

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This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm2.

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As interests in air quality monitoring related to environmental pollution and industrial safety increase, demands for gas sensors are rapidly increasing. Among various gas sensor types, the semiconductor metal oxide (SMO)-type sensor has advantages of high sensitivity, low cost, mass production, and small size but suffers from poor selectivity. To solve this problem, electronic nose (e-nose) systems using a gas sensor array and pattern recognition are widely used. However, as the number of sensors in the e-nose system increases, total power consumption also increases. In this study, an ultra-low-power e-nose system was developed using ultraviolet (UV) micro-LED (µLED) gas sensors and a convolutional neural network (CNN). A monolithic photoactivated gas sensor was developed by depositing a nanocolumnar In2O3 film coated with plasmonic metal nanoparticles (NPs) directly on the µLED. The e-nose system consists of two different µLED sensors with silver and gold NP coating, and the total power consumption was measured as 0.38 mW, which is one-hundredth of the conventional heater-based e-nose system. Responses to various target gases measured by multi-µLED gas sensors were analyzed by pattern recognition and used as the training data for the CNN algorithm. As a result, a real-time, highly selective e-nose system with a gas classification accuracy of 99.32% and a gas concentration regression error (mean absolute) of 13.82% for five different gases (air, ethanol, NO2, acetone, methanol) was developed. The µLED-based e-nose system can be stably battery-driven for a long period and is expected to be widely used in environmental internet of things (IoT) applications.

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Nowadays, indoor positioning (IP) is a relevant aspect in several scenarios within the Internet of Things (IoT) framework, e.g., Industry 4.0, Smart City and Smart Factory, in order to track, amongst others, the position of vehicles, people or goods. This paper presents the realization and testing of a low power sensor node equipped with long range wide area network (LoRaWAN) connectivity and providing 2D Visible Light Positioning (VLP) features. Three modulated LED (light emitting diodes) sources, the same as the ones commonly employed in indoor environments, are used. The localization feature is attained from the received light intensities performing optical channel estimation and lateration directly on the target to be localized, equipped with a low-power microcontroller. Moreover, the node exploits a solar cell, both as optical receiver and energy harvester, provisioning energy from the artificial lights used for positioning, thus realizing an innovative solution for self-sufficient indoor localization. The tests performed in a ~1 m2 area reveal accurate positioning results with error lower than 5 cm and energy self-sufficiency even in case of radio transmissions every 10 min, which are compliant with quasi-real time monitoring tasks.

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This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 µW, achieving ultra-low-power operation.

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This paper reviews and analyses the design of popular radio frequency energy harvesting systems and proposes a method to qualitatively and quantitatively analyze their circuit architectures using new square-wave approximation method. This approach helps in simplifying design analysis. Using this analysis, we can establish no load output voltage characteristics, upper limit on rectifier efficiency, and maximum power characteristics of a rectifier. This paper will help guide the design of RF energy harvesting rectifier circuits for radio frequency identification (RFIDs), the Internet of Things (IoTs), wearable, and implantable medical device applications. Different application scenarios are explained in the context of design challenges, and corresponding design considerations are discussed in order to evaluate their performance. The pros and cons of different rectifier topologies are also investigated. In addition to presenting the popular rectifier topologies, new measurement results of these energy harvester topologies, fabricated in 65nm, 130nm and 180nm CMOS technologies are also presented.

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The rapid development of Internet of Things (IoT) applications calls for light-weight IoT sensor nodes with both low-power consumption and excellent task execution efficiency. However, in the existing system framework, designers must make trade-offs between these two. In this paper, we propose an "edge-to-end integration" design paradigm, Butterfly, which assists sensor nodes to perform sensing tasks more efficiently with lower power consumption through their (high-performance) network infrastructures (i.e., a gateway). On the one hand, to optimize the power consumption, Butterfly offloads the energy-intensive computational tasks from the nodes to the gateway with only microwatt-level power budget, thereby eliminating the power-consuming Microcontroller (MCU) from the node. On the other hand, we address three issues facing the optimization of task execution efficiency. To start with, we buffer the frequently used instructions and data to minimize the volume of data transmitted on the downlink. Furthermore, based on our investigation on typical sensing data structures, we present a novel last-bit transmission and packaging mechanism to reduce the data amount on the uplink. Finally, we design a task prediction mechanism on the gateway to support efficient scheduling of concurrent tasks on multiple MCU-free Butterfly nodes. The experiment results show that Butterfly can speed up the task rate by 4.91 times and reduce the power consumption of each node by 94.3%, compared to the benchmarks. In addition, Butterfly nodes have natural security advantages (e.g., anti-capture) as they offload the control function with all application information up to the gateway.

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The rapid evolution of Internet of Things (IoT) applications, such as e-health and the smart ecosystem, has resulted in the emergence of numerous security flaws. Therefore, security protocols must be implemented among IoT network nodes to resist the majority of the emerging threats. As a result, IoT devices must adopt cryptographic algorithms such as public-key encryption and decryption. The cryptographic algorithms are computationally more complicated to be efficiently implemented on IoT devices due to their limited computing resources. The core operation of most cryptographic algorithms is the finite field multiplication operation, and concise implementation of this operation will have a significant impact on the cryptographic algorithm's entire implementation. As a result, this paper mainly concentrates on developing a compact and efficient word-based serial-in/serial-out finite field multiplier suitable for usage in IoT devices with limited resources. The proposed multiplier structure is simple to implement in VLSI technology due to its modularity and regularity. The suggested structure is derived from a formal and systematic technique for mapping regular iterative algorithms onto processor arrays. The proposed methodology allows for control of the processor array workload and the workload of each processing element. Managing processor word size allows for control of system latency, area, and consumed energy. The ASIC experimental results indicate that the proposed processor structure reduces area and energy consumption by factors reaching up to 97.7% and 99.2%, respectively.

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With the introduction of Internet of Things (IoT) technology in several sectors, wireless, reliable, and energy-saving communication in distributed sensor networks are more important than ever. Thereby, wake-up technologies are becoming increasingly important as they significantly contribute to reducing the energy consumption of wireless sensor nodes. In an indoor environment, the use of wireless sensors, in general, is more challenging due to signal fading and reflections and needs, therefore, to be critically investigated. This paper discusses the performance analysis of wake-up receiver (WuRx) architectures based on two low frequency (LF) amplifier approaches with regard to sensitivity, power consumption, and package error rate (PER). Factors that affect systems were compared and analyzed by analytical modeling, simulation results, and experimental studies with both architectures. The developed WuRx operates in the 868 MHz band using on-off-keying (OOK) signals while supporting address detection to wake up only the targeted network node. By using an indoor setup, the signal strength and PER of received signal strength indicator (RSSI) in different rooms and distances were determined to build a wireless sensor network. The results show a wake-up packets (WuPts) detection probability of about 90% for an interior distance of up to 34 m.