RESUMEN
A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading 'ON' current decreases. To prevent performance degradation, two ways to compensate for current level were suggested.
RESUMEN
The effect of the work-function variation (WFV) of metal-oxide-semiconductor field-effect transistor (MOSFET) gates on a monolithic 3D inverter (M3DINV) structure is investigated in the current paper. The M3DINV has a structure in which MOSFETs are sequentially stacked. The WFV effect of the top- and bottom-tier gates on the M3DINV is investigated using technology computer-aided design (TCAD) and a Monte-Carlo sampling simulation of TCAD. When the interlayer dielectric thickness (TILD) changes from 5 to 100 nm, electrical parameters, such as the threshold voltage, subthreshold swing, on-current, and off-current of the top-tier N-MOSFET and the parameter changes by the change in gate voltage of the bottom-tier P-MOSFET, are investigated. As TILD decreases below about 30 nm, the means and standard deviations of the electrical parameters rapidly increase. This means that the coupling and its distribution are relatively large in the regime and thus should be well considered for M3D circuit simulation. In addition, due to the increase in standard deviation, the WFV effect of both the top- and bottom-tier MOSFET gates was observed to be greater than those of only the top-tier MOSFET gates and only the bottom-tier MOSFET gates.