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The realization of brain-scale spiking neural networks (SNNs) is impeded by power constraints and low integration density. To address these challenges, multi-core SNNs are utilized to emulate numerous neurons with high energy efficiency, where spike packets are routed through a network-on-chip (NoC). However, the information can be lost in the NoC under high spike traffic conditions, leading to performance degradation. This work presents NEXUS, a 16-core SNN with a diamond-shaped NoC topology fabricated in 28-nm CMOS technology. It integrates 4096 leaky integrate-and-fire (LIF) neurons with 1M 4-bit synaptic weights, occupying an area of 2.16 mm2. The proposed NoC architecture is scalable to any network size, ensuring no data loss due to contending packets with a maximum routing latency of 5.1µs for 16 cores. The proposed congestion management method eliminates the need for FIFO in routers, resulting in a compact router footprint of 0.001 mm2. The proposed neurosynaptic core allows for increasing the processing speed by up to 8.5× depending on input sparsity. The SNN achieves a peak throughput of 4.7 GSOP/s at 0.9 V, consuming a minimum energy per synaptic operation (SOP) of 3.3 pJ at 0.55 V. A 4-layer feed-forward network is mapped onto the chip, classifying MNIST digits with 92.3% accuracy at 8.4Kclassification/ s and consuming 2.7-µJ/classification. Additionally, an audio recognition task mapped onto the chip achieves 87.4% accuracy at 215-µJ/classification.

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In this work, we present fabricated magnetic tunnel junctions (MTJs) that can serve as magnetic memories (MMs) or vortex spin-torque nano-oscillators (STNOs) depending on the device geometry. We explore the heating effect on the devices to study how the performance of a neuromorphic computing system (NCS) consisting of MMs and STNOs can be enhanced by temperature. We further applied a neural network for waveform classification applications. The resistance of MMs represents the synaptic weights of the NCS, while temperature acts as an extra degree of freedom in changing the weights and TMR, as their anti-parallel resistance is temperature sensitive, and parallel resistance is temperature independent. Given the advantage of using heat for such a network, we envision using a vertical-cavity surface-emitting laser (VCSEL) to selectively heat MMs and/or STNO when needed. We found that when heating MMs only, STNO only, or both MMs and STNO, from 25 to 75 °C, the output power of the STNO increases by 24.7%, 72%, and 92.3%, respectively. Our study shows that temperature can be used to improve the output power of neural networks, and we intend to pave the way for future implementation of a low-area and high-speed VCSEL-assisted spintronic NCS.

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Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

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This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 µVrms, and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 µm standard CMOS technology and consumes 4.5 µW while occupying 1.125 mm2.

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Objective. Therapeutic intervention in neurological disorders still relies heavily on pharmacological solutions, while the treatment of patients with drug resistance remains an unresolved issue. This is particularly true for patients with epilepsy, 30% of whom are refractory to medications. Implantable devices for chronic recording and electrical modulation of brain activity have proved a viable alternative in such cases. To operate, the device should detect the relevant electrographic biomarkers from local field potentials (LFPs) and determine the right time for stimulation. To enable timely interventions, the ideal device should attain biomarker detection with low latency while operating under low power consumption to prolong battery life.Approach. Here we introduce a fully-analog neuromorphic device implemented in CMOS technology for analyzing LFP signals in anin vitromodel of acute ictogenesis. Neuromorphic networks have progressively gained a reputation as low-latency low-power computing systems, which makes them a promising candidate as processing core of next-generation implantable neural interfaces.Main results. The developed system can detect ictal and interictal events with ms-latency and with high precision, consuming on average 3.50 nW during the task.Significance. The work presented in this paper paves the way to a new generation of brain implantable devices for personalized closed-loop stimulation for epilepsy treatment.

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A low-power mixed-signal IC for implantable pacemakers is presented. The proposed system features three independent intracardiac signal readout channels with pulse-width-modulated outputs. Also, the proposed system is capable of measuring the amplitude and phase of the bioimpedance with pulse-width-modulated outputs for use in rate adaptive pacemakers. Moreover, a stimulation system is embedded, offering 16 different amplitudes from 1 to 7.8 V. A backscattering transmitter transfers the output signals outside the body with very little power consumption. The proposed low-power mixed-signal IC is fabricated in a 0.18-µm HV CMOS process and occupies 2.38 mm2. The biopotential channels extract the heart signals with 9.2 effective number of bits and the bioimpedance channels measure the amplitude and phase of the heart impedance with 1.35 Ωrms accuracy. The complete IC consumes only 4.2 µA from a 1-V power supply.

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This paper presents an implantable bio-impedance measurement system for cardiac pacemakers. The fully integrated system features a low power analog front-end and pulse width modulated output. The bio-impedance readout benefits from voltage to time conversion to achieve a very low power consumption for wirelessly transmitting the data outside the body. The proposed IC is fabricated in a 0.18 µm CMOS process and is capable of measuring the bio-impedance at 2 kHz over a wide dynamic range from to with accuracy and maximum current injection while consuming just from a 1 V supply.

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