RESUMEN
For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.
RESUMEN
While observing the transfer characteristics of a-IGZO TFTs, it was noticed that a hump occurred in the subthreshold regime after light and bias stress. This study analyzes the mechanism of the hump occurrence. It was determined that hump characteristics were related with parasitic TFTs which formed at the peripheral edges parallel with the channel direction. It seems that the negative shift of the transfer characteristics of parasitic TFTs was larger than that of the main TFT under light and bias stress. Therefore, the difference in the negative shift between the main TFT and the parasitic TFT was the origin of the hump occurrence. We investigated the instability of a-IGZO TFTs under negative gate bias with light illumination for various channel structures in order to verify the above mechanism.