RESUMEN
We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects.
RESUMEN
We demonstrate depletion-mode carrier-plasma optical modulators fabricated in a bulk complementary metal-oxide semiconductor (CMOS), DRAM-emulation process. To the best of our knowledge, these are the first depletion-mode modulators demonstrated in polycrystalline silicon and in bulk CMOS. The modulators are based on novel optical microcavities that utilize periodic spatial interference of two guided modes to create field nulls along waveguide sidewalls. At these nulls, electrical contacts can be placed while preserving a high optical Q. These cavities enable active devices in a process with no partial silicon etch and with lateral p-n junctions. We demonstrate two device variants at 5 Gbps data modulation rate near 1610 nm wavelength. One design shows 3.1 dB modulation depth with 1.5 dB insertion loss and an estimated 160 fJ/bit energy consumption, while a more compact device achieves 4.2 dB modulation depth with 4.0 dB insertion loss and 60 fJ/bit energy consumption. These modulators represent a significant breakthrough in enabling active photonics in bulk silicon CMOS--the platform of the majority of microelectronic logic and DRAM processes--and lay the groundwork for monolithically integrated CMOS-to-DRAM photonic links.