RESUMEN
Complementary metal-oxide semiconductor (CMOS) image sensor sensitivity in the near-infrared spectrum is limited by the absorption length in silicon. To deal with that limitation, we evaluate the implementation of a polysilicon nano-grating inside a pixel, at the transistor gate level of a 90 nm standard CMOS process, through opto-electrical simulations. The studied pixel structure involves a polysilicon nano-grating, designed with the fabrication layer of the transistor gate, which does not require any modifications in the process flow. The diffraction effect of the nano-grating increases the length of the light path in the photosensitive area and thus increases the photoelectric conversion efficiency. The nano-grating is integrated in combination with deep trench isolations to reduce cross talk between pixels. Coupled optical and electrical simulations report 33% external quantum efficiency improvement and 7% cross talk reduction at 850 nm.
RESUMEN
The leakage current non-uniformity, as well as the leakage current random and discrete fluctuations sources, are investigated in pinned photodiode CMOS image sensor floating diffusions. Different bias configurations are studied to evaluate the electric field impacts on the FD leakage current. This study points out that high magnitude electric field regions could explain the high floating diffusion leakage current non-uniformity and its fluctuation with time called random telegraph signal. Experimental results are completed with TCAD simulations allowing us to further understand the role of the electric field in the FD leakage current and to locate a high magnitude electric field region in the overlap region between the floating diffusion implantation and the transfer gate spacer.