RESUMEN
Ptychographic imaging techniques can be coupled with tomographic image reconstruction techniques to obtain cross-sectional 3D images with resolution on the nanometer scale. However, such ptychographic x-ray computed tomography (PXCT) techniques require the collection of a large number of diffraction patterns. This work derives a set of equations that can be used to calculate the rate at which data can be collected given an experimental setup. It also determines the computational system requirements needed to process ptychographic data in real time as soon as it has been collected. This will expedite the ptychography step of PXCT. These theoretical results are then applied to performance data collected from reconstructing simulated diffraction patterns in order to determine the computational resources needed for real-time ptychographic processing for representative experimental setups. All of our results are independent of any specific ptychographic reconstruction algorithm.
RESUMEN
Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 µm thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 µm thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.
RESUMEN
The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring and complexity. We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.