RESUMEN
The possible use of electrostrictive materials for information processing devices has been widely discussed because it could allow low-power logic operation by overcoming the fundamental limit of subthreshold swing greater than 60 mV/decade in conventional MOSFETs. However, existing proposals for electrostrictive FET applications typically adopt approaches that are entirely theoretical and simulative, thus lacking practical insights into how an electrostrictive material can be best interfaced with a channel material. Here we propose an electrostrictive FET device, involving the epitaxial oxide heterostructure as an ideal material platform for maximum strain transfer. The ON/OFF switching occurs due to a stress-induced concentration change of oxygen vacancies in the memristive oxide channel layer. Based on finite-element simulations, we show that the application of a minimal gate voltage bias can induce stress in the channel layer as high as 108 N/m2 owing to the epitaxial interface between the electrostrictive and memristive oxide layers. Conductive AFM experiments further support the feasibility of the proposed device by demonstrating the stress-induced conductivity modulation of a perovskite oxide thin film, SrTiO3, that is well known to serve as the substrate for epitaxial growth of other functional oxide layers.
RESUMEN
PCM (phase-change memory) is an important class of data storage, operating based on the Joule heating-induced reversible switching of chalcogenide alloys. Nanoscale PCM often requires advanced microfabrication techniques such as dry (plasma) etching, but the possible impacts of process damages or imperfections on the device performance still remain relatively unexplored. This is critical because some chemical etching species are known to cause over-etching with rough edge onto the sidewall of a phase-change material. It is also possible that the phase-change material experiences a composition change due to etching-induced re-deposition of by-products or thermal stress. In this study, a finite-element simulation is performed to understand the effect of dry etching on the RESET characteristics of a nanoscale PCM device to provide a guideline on the PCM manufacturing and cell design.